The present invention relates generally to semiconductor memory and, more particularly, to architectures for a ferroelectric memory and methods of reading such ferroelectric memory.
Exemplary known semiconductor memory include dynamic random access memory (DRAM), static random access memory (SRAM), electrically programmable read only memory (EPROM), flash memory, and ferromagnetic semiconductor memory devices. SRAM and DRAM devices are volatile, and require continuous power for data retention. When power is removed from these volatile devices, data is lost.
Unlike the volatile devices, nonvolatile memory retains data in the absence of power. Exemplary nonvolatile memory include the magneto-resistive, ferro-magnetic, and ferroelectric memory devices. Recently, some manufactures of nonvolatile memory have been working to improve ferroelectric memory devices.
Referencing FIGS. 1 and 2, an exemplary known ferroelectric cell 10 comprises ferroelectric material 16 sandwiched between first and second electrodes 12, 14, such as, for example, wordline 20 and bitline 22 of a known ferroelectric memory array. The spontaneous polarization Ps vector characterizes an alignment of domains of the ferroelectric material as influenced by an electric field. Upon removal of the electric field, a remanent polarization Pr remains. Applying a switching level electric field of opposite polarity reverses the polarization orientation.
The polarization versus voltage properties of an exemplary ferroelectric cell is characterized by hysteresis curve 24 of FIG. 3. The hysteresis curve crosses vertical axis 28 at two locations 21, 23 representative of the remanent polarizations associated with the “0” (zero) and “1” (one) state storage conditions. In FIG. 3, curve 24 shows remanent polarization Pr for the memory under zero bias at position 21 with a magnitude less than that of the saturation polarization Ps at bias position 25. This is understood to result because some of the domains of the ferroelectric do not stay aligned when the applied voltage bias is reduced, e.g., from the saturation level Vs to zero.
Further referencing FIGS. 2-3, by applying a negative voltage −Vs to wordline 20 relative bitline 22, the cell's polarization is set to its negative orientation (following path 34 of curve 24 to position 27) for storing a “one” state condition. Upon removing the applied voltage, the cell's negative polarization remains (path 36 to remanent position 23). Thereafter, applying a positive voltage Vs reverses the cells polarization state, which “one” to “zero” polarization reversal is accompanied by an associated charge release. In contrast, a cell of a zero state would not provide such charge release with application of positive Vs. This difference in the released charge between the “one” and “zero” states provides the fundamental principle for reading a ferroelectric cell.
Ferroelectrics also exhibit resilience, wherein a ferroelectric cell can restore a remanent polarization despite a small disturbance. For example, assuming a one state storage condition for a ferroelectric cell, as represented by remanent polarization position 23 of hysteresis curve 24, a small voltage disturbance of Vs/3 provides a small polarization shift 40 along path 38. However, once the voltage is removed, domains of the ferroelectric cell realign their orientations to that of the cell's overall orientation, as illustrated by return path 39 of hysteresis curve 24.